All IPs > Memory & Logic Library > I/O Library > Mixed Digital and Analog Library, compatible with I2C and I3C Protocols in TSMC 65nm
From Certus Semiconductor
This library is a mixed Digital and Analog library built for the TSMC 65nm process. It is based around a Fail-Safe General
Purpose Input/Output (FSGPIO) cell that is compatible with both I2C and I3C protocols. The FSGPIO operates with a power
supply of 1.0 to 1.2V and can tolerate external signals up to 3.3V. The library contains all the power, ground, and ESD cells
to support the FSGPIO as well as an Analog I/O cell. The cells are laid out in an inline wirebond format.
| Foundry | Process Nodes |
|---|---|
| TSMC |
65nm |
| Class | Value |
|---|---|
| Categories |
Memory & Logic Library > I/O Library Interface Controller & PHY > I2C |
| PDK Version | Various |
| Silicon Validated | Pending |
| In Production? | No |
| Metallization | 1P7M_5X1Z0U_ALRDL |
| Key I/O Standards | I3C, I2C, DDC, CEC, SMBus |
| Availability | All Countries & Regions |
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