All IPs > Interface Controller & PHY > USB > LPDDR4/4X/5 Secondary/Slave PHY
The secondary or slave PHY for LPDDR4/4X/5 is designed to serve memory-side applications, facilitating efficient communication between diverse devices and processing units in AI and in-memory computing. Its low power, high-speed nature makes it ideal for dynamic environments adhering to current JEDEC standards.
| Foundry | Process Nodes |
|---|---|
| TSMC |
7nm |
| Class | Value |
|---|---|
| Categories |
Interface Controller & PHY > USB Memory Controller & PHY > DDR Interface Controller & PHY > AMBA AHB / APB/ AXI Memory Controller & PHY > SDRAM Controller Memory Controller & PHY > eMMC Memory Controller & PHY > Mobile DDR Controller Memory Controller & PHY > NAND Flash |
| Availability | All Countries & Regions |
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