All IPs > Interface Controller & PHY > USB > LPDDR4/4X/5 Secondary/Slave PHY
This Secondary/Slave PHY is intended for the memory side, offering high-speed, low-power protocols for data transfer. Following the JEDEC standards for LPDDR4/4X/5, it promotes efficient communication in various devices, especially AI and memory-intensive solutions. Although designed for TSMC's 7nm technology, its flexible architecture allows adaptation across different processes and memory configurations.
| Foundry | Process Nodes |
|---|---|
| TSMC |
7nm |
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