All IPs > Memory Controller & PHY > DDR > LPDDR4/4X/5 PHY
This PHY is designed to support high-speed LPDDR4/4X/5 memory interfaces. It is optimized for low power consumption and can be integrated into a wide range of devices such as AI coprocessors and in-memory computing solutions. The design adheres to JEDEC standards, making it suitable for various memory types, including DRAM and emerging non-volatile memories.
| Foundry | Process Nodes |
|---|---|
| TSMC |
7nm |
| Class | Value |
|---|---|
| Categories |
Memory Controller & PHY > DDR Interface Controller & PHY > AMBA AHB / APB/ AXI Memory Controller & PHY > SDRAM Controller Memory Controller & PHY > eMMC Memory Controller & PHY > Mobile DDR Controller Memory Controller & PHY > NAND Flash |
| Availability | All Countries & Regions |
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