The Low Latency Ethernet MAC core provides a vital solution for systems needing quick and effective network connectivity over 10G and 25G Ethernet protocols. Developed in collaboration with Fraunhofer HHI, this IP core supports high-speed networking with very low latency by efficiently managing data frames in FPGA-based systems.
It supports the AXI4-Stream protocol, ensuring seamless data transmission and reception processes while optimizing resource usage. The core includes crucial mechanisms such as frame-padding for short frames, VLAN support, and a checksum feature for ensuring data integrity at full line rates. These features make it ideal for handling such network protocols within constrained latency budgets.
Intended for a wide array of networking applications, this IP core offers considerable flexibility and customization options, including user-defined settings for maximum frame lengths. Applications span data centers, high-speed trading platforms, and real-time communication systems where low latency is a significant advantage. Its delivery as an integrated, licensable IP core, along with supporting design services, provides comprehensive support for system architects requiring robust Ethernet solutions.
