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All IPs > Memory Controller & PHY > SDRAM Controller > JTAG Test and Configuration

JTAG Test and Configuration

From Intellitech Corp.

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Description

The JTAG Test and Configuration solution by Intellitech leverages IEEE 1149.1/JTAG techniques to provide an extensive set of boundary scan test tools for PCBs. This solution empowers design teams with the capability to not only perform high-quality self-testing but also to undertake in-field reconfiguration of products. By using patented plug-and-play scan components, Intellitech reduces BOM costs while enhancing product functionalities. The Eclipse Test Development Environment is a comprehensive toolkit that allows seamless integration of debug and test processes into PCB designs, significantly lowering development time. The suite supports concurrent testing, eliminating production bottlenecks by executing tests across multiple PCBs simultaneously. This makes the Intellitech solution ideal for deployment in both prototyping and high-volume production environments.

Features
  • Supports IEEE 1149.1 standard
  • Integrates with Eclipse Test Development Environment
  • Concurrent testing capabilities
Foundries & Process Nodes
Foundry Process Nodes
TSMC 180nm
Tech Specs
Applications
  • High-volume PCB testing
  • In-field product reconfiguration
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