The JTAG Test and Configuration solution by Intellitech provides a robust framework for using IEEE 1149.1 (JTAG) techniques to lower system costs and enhance product testability and configurability. This patented infrastructure Intellectual Property enables design teams to develop high-quality, self-testable products that can be reconfigured in the field. By integrating plug-and-play scan components, it reduces design complexity, shortens development time, and provides capabilities that add significant value for customers.
This solution supports a comprehensive range of tools for boundary scan, flash programming, and FPGA configuration, integrated into Intellitech's Eclipse Test Development Environment. This environment offers a complete suite for 1149.1-based testing and in-system configuration of complex PCBs and systems, reducing debug time and enhancing prototype testing efficiency. The capability to toggle and observe logic values directly enhances the ease and effectiveness of debugging processes.
The tools included in this solution, such as the Scan Executive and accompanying production test platforms, ensure PCB shorts and opens can be identified with minimal effort, streamlining the testing process. Concurrent JTAG testing allows for the testing of multiple PCBs or System Under Test units simultaneously, optimizing throughput without creating production bottlenecks. Overall, this solution drastically improves testing experiences and operational efficiencies in high-volume manufacturing environments.
