NetTimeLogic provides specialized IRIG products designed for effective time distribution using standard IRIG protocols. The IRIG Master core outputs precise time signals, facilitating coordinated time distribution across systems without relying on external software conditions. Correspondingly, the IRIG Slave core reads and synchronizes an incoming IRIG signal to the local clock system. Both the Master and Slave cores are implemented strictly in hardware, ensuring minimal overhead and compatibility with various FPGA setups. Designed for robustness, these cores support DCLS and AC encoding, leveraging external DAC and ADC components. This hardware-only design supports critical applications requiring synchronized time across diverse platforms, from scientific measurements to industrial automation.
