Bitec's HDMI 2.1b IP Core is engineered to enable seamless HDMI connectivity in both FPGA and ASIC devices. Designed with a high level of parameterization, it supports uncompressed 8K60 4:2:0 video formats as well as compressed formats through Display Stream Compression (DSC). The core is compatible with a range of HDMI standards including 2.0b, 1.4a, and DVI, providing flexibility across various interface needs. Audio and auxiliary data are managed efficiently, allowing for enhanced development and testing capabilities of HDMI interfaces, while also accommodating advanced video formats and control packets.
This IP core supports deep-color modes up to 16 bits and includes features like Audio Return Channel (ARC/eARC) and High-bandwidth Digital Content Protection (HDCP 1.4/2.3). Designed to harmonize with third-party SERDES, it enables rapid deployment of high-performance image processing systems. The HDMI 2.1b IP core can be configured to work in parallel with Bitec’s DisplayPort IP Core, facilitating DP++ compatibility for combined DisplayPort and HDMI connectivity.
Offering comprehensive support for various video and audio formats, the core is geared towards premium user experiences, supporting multiple-channel audio and raw data streams. The optional DSC feature broadens its application to demanding high-resolution displays, with capabilities to ‘share’ the DSC core for optimal operation in systems integrating both HDMI and DisplayPort interfaces.
