The embedded FPGA (eFPGA) from ADICSYS is a groundbreaking solution designed for seamless integration within ASICs and SOCs. This technologically independent FPGA is fully compatible with standard RTL design flows, making it a versatile choice for a wide variety of semiconductor applications. It allows for customizations in dimensions and architecture, including LUT count and routing density, tailored to meet specific area, performance, or power constraints.
The eFPGA by ADICSYS promises high levels of flexibility and adaptability by incorporating a Verilog-based programmable IP featuring synthesizable RTL and constraint files. This is complemented by ADICSYS's proprietary compilation tool, Acompile, as well as a bitstream loader and built-in self-test (BIST) program. It even offers the option of delivering a hard block, such as GDSII, for specific design kits, ensuring bespoke integration suited to distinct customer requirements.
Engineered to enhance system capability, ADICSYS's eFPGA significantly reduces time to market by simplifying design verification processes. It mitigates risks related to bugs and offers post-silicon flexibilities, ensuring that developments remain adaptable until tape-out. With support for extensive use of standard cells, it facilitates risk reduction by eliminating the need for unique silicon-proofing with each new instance, making recent technology nodes more accessible.
