The DHDLC IP core provides versatile support for widely used HDLC transmission protocol. It manages the bit stuffing/unstuffing process, address appending and detection as also supports both CRC16 and CRC32 computation among the other features. The presence of separate receiver and transmitter FIFO buffers as also the maskable interrupt and DMA interface request will increase the system performance by reducing the CPU overload. Although the DHDLC's main advantage is high scalability, which ensures that our core functionality will meet the requirements of both high-ended and deep embedded solutions. It can be provided with the small 8-bit SRAM like interface, 32-bit full AXI4 slave interface with burst support, AXI4Lite interface as also AHB and APB slave interfaces. The optional Frame Status Buffer stores the information about the frames sizes and error conditions. The sizes of both receiver and the transmitter FIFO buffers are configurable and not used features can be removed before the synthesis process. All gathered makes it an ideal choice for very popular higher level protocol implementations like PPP(Point-to-Point), X.25, V.42, LAP-B, SDLC, ISDN and many others.
