Overview:
The DDR5 RCD Controller is a registering clock driver utilized in DDR5 RDIMMs and LRDIMMs. It buffers the Command/Address (CA) bus, chip selects, and clock signals between the host controller and DRAMs. Additionally, it establishes a BCOM bus to control data buffers in LRDIMMs.
Key Features:
Compliance with JEDEC's JESD82-511
Maximum SCL Operating speed of 12.5MHz in I3C mode
DDR5 server speeds up to 4800MT/s
Dual-channel configuration with 32-bit data width per channel
Support for power-saving mechanisms
Rank 0 & rank 1 DIMM configurations
Loopback and pass-through modes
BCOM sideband bus for LRDIMM data buffer control
In-band Interrupt support
Packet Error Check (PEC)
CCC Packet Error Handling
Error log register
Parity Error Handling
Interrupt Arbitration
I2C Fast-mode Plus (FM+) and I3C Basic compatibility
Switch between I2C mode and I3C Basic
Clearing of Status Registers
Compliance with JESD82-511 specification
I3C Basic Common Command Codes (CCC)
Applications:
RDIMM
LRDIMM
AI (Artificial Intelligence)
HPC (High-Performance Computing)
Data-intensive applications
