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All IPs > Memory Controller & PHY > DDR > DDR5 CKD 01 - Clock Driver

DDR5 CKD 01 - Clock Driver

From MAXVY Technologies Pvt Ltd

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Description

The DDR5CKD01 is a registering clock driver used on DDR5 CUDIMMs, CSODIMMs, and CAMM. Its primary function is to buffer the DDR clock between the Host controller and the DRAMs

Deliverables
Soft IP
  • Compliance
  • Synthesizable RTL
  • Verilog integration testbench
  • Sample synthesis script and constraints
  • Sample simulation script
  • Datasheet
  • Verification test bench and test vectors
Features
  • Compliance as per JEDEC’s JESD82-531B - Version 1.21
  • CKD PLL modes PLL ByPass Mode, Single PLL Mode, Dual PLL Mode.
  • Clock Stop Operation
  • PLL Modes output frequency range 1000 MHz to 4600 MHz supported
  • PLL Modes Frequency change supported.
  • LID’s determination based on ZQCAL RL value.
  • Sideband Interface I3C mode up to 12.5 MHz and I2C mode up to 1 MHz speed supported
  • Parity Check is enabled
  • Packet Error Check is supported (PEC)
  • Supported Switch from I2C to I3C Basic Mode and vice versa
  • Support CKD write and read operations with or without PEC enabled
  • In-band Interrupt (IBI)
  • Interrupt Arbitration
  • I3C Basic Common Command Codes (CCC) ENEC DISEC RSTDAA SETAASA GETSTATUS DEVCAP SETHID DEVCTRL
  • Bus Reset, Bus clear supported
  • Clearing Status Register
  • Packet Error Check & Parity Error Handling
  • CCC Packet Error Handling
Tech Specs
Class Value
Categories Memory Controller & PHY > DDR
Compliant Standard JEDEC’s JESD82-531B - Version 1.21
Availability US, Canada, UK & EU Only
Image Gallery
DDR5 CKD 01 - Clock Driver
Applications
  • DDR5 CUDIMM
  • CSODIMM
  • CAMM
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