The CVC Verilog Simulator is an advanced electronic design automation tool designed to simulate models of electronic hardware based on the IEEE 1364 2005 Verilog HDL standard. CVC stands out in the field by converting Verilog code into native X86_64 machine instructions, which can be executed as straightforward Linux binaries. This sophisticated simulation suite offers exceptional speed and performance, making it a highly competitive choice in the realm of Verilog simulation products.
CVC excels in handling vast gate and RTL capacities, and its 64-bit simulation capabilities deliver significantly faster results than their 32-bit counterparts on modern hardware, albeit with an increase in binary file size. This adaptability makes it ideal for machine-generated Verilog simulation, and the tool features an innovative X-propagation synthesizable Verilog expression evaluation algorithm. CVC can operate in both compiled and interpreted modes, allowing for quick elaboration and fast execution depending on the design phase and complexity.
The simulator includes comprehensive support for Verilog's standard functionalities, including full PLI (vpi_, dpi_, acc_, tf_) support and a highly efficient interface for integration with C/C++ applications. Moreover, CVC offers advanced state dump formats and parallel FST generation to enhance performance and debugging. Its compliance with IEEE Verilog 1364-2005 standards, along with its easy-to-use compilation processes, underscores the simulator's reliability and broad applicability in diverse design environments.
