The CVC Verilog Simulator is an advanced tool developed to meet the rigorous demands of modern electronic design automation. Built to comply fully with the IEEE 1364-2005 Verilog HDL standard, it is capable of translating Verilog code into native X86_64 machine instructions, providing high-speed simulation performance on Linux systems.
CVC is particularly noted for its fast native compiled simulations, handling extensive gate and RTL capacities, which are optimized for modern 64-bit hardware configurations. This makes CVC ideal for handling machine-generated Verilog simulations, offering solutions tailored to efficiently execute complex electronic models. The simulator includes an innovative X-propagation algorithm for Verilog expression evaluation, which enhances synthesizability and reliability of simulations.
Designed to cater to versatile requirements, CVC allows switching between compiled and interpreted modes, allowing quick elaboration of designs initially, and transitioning to high-speed simulation as needed. It supports comprehensive design state dump formats, like VCD, EVCD, and FST, ensuring compatibility and ease of use, particularly with tools like GTKWave for waveform analysis. Additionally, its full support for PLI (vpi_, dpi_, acc_, tf_) interfaces provides a seamless and high-performance integration with C/C++ codebases.
CVC supports features such as toggle coverage and parallel state dumping, optimized for dual-core processing, creating a streamlined design and simulation experience. With its practical approach to licensing and user engagement, including educational materials for deeper understanding, CVC stands out as an accessible yet robust simulation software.
