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All IPs > Processor > AI Processor > Chimera GPNPU

Chimera GPNPU

From Quadric

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Description

Chimera GPNPU provides a groundbreaking architecture, melding the efficiency of neural processing units with the flexibility and programmability of processors. It supports a full range of AI and machine learning workloads autonomously, eliminating the need for supplementary CPUs or GPUs. The processor is future-ready, equipped to handle new and emerging AI models with ease, thanks to its C++ programmability.

What makes Chimera stand out is its ability to manage a diverse array of workloads within a singular processor framework that combines matrix, vector, and scalar operations. This harmonization ensures maximum performance for applications across various market sectors, such as automotive, mobile devices, and network edge systems. These capabilities are designed to streamline the AI development process and facilitate high-performance inference tasks, crucial for modern gadget ecosystems.

The architecture is fully synthesizable, allowing it to be implemented in any process technology, from current to advanced nodes, adjusting to desired performance targets. The adoption of a hybrid Von Neuman and 2D SIMD matrix design supports a broad suite of DSP operations, providing a comprehensive toolkit for complex graph and AI-related processing.

Features
  • Handles matrix, vector, and scalar operations seamlessly
  • Unified processor architecture for diverse AI/ML models
  • Fully synthesizable for various process technologies
Tech Specs
Class Value
Categories Processor > AI Processor
Platform Level IP > Processor Core Independent
Processor > CPU
Processor > DSP Core
Graphic & Peripheral > GPU
Multimedia > VGA
Processor > Vision Processor
Platform Level IP > Multiprocessor / DSP
Interface Controller & PHY > AMBA AHB / APB/ AXI
Platform Level IP > Processor Core Dependent
Processor > Microcontroller
Processor > Building Blocks
Processor > Processor Cores
Processor > IoT Processor
Network on Chip > Network on Chip
Instruction Word 64b
Pipeline Stages 7-stage, in-order pipeline
L2 Memory 1MB to 16MB configurable
Instruction Cache 64/128/256K
Power Optimization Compiler-driven, fine-grained clock gating
Matrix Architecture Hybrid Von Neuman + 2D SIMD
Availability All Countries & Regions
Applications
  • Automotive systems
  • Mobile and edge computing devices
  • Digital home applications
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