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All IPs > Processor > AI Processor > Chimera GPNPU

Chimera GPNPU

From Quadric

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Description

Quadric's Chimera GPNPU is an adaptable processor core designed to respond efficiently to the demand for AI-driven computations across multiple application domains. Offering up to 864 TOPS, this licensable core seamlessly integrates into system-on-chip designs needing robust inference performance. By maintaining compatibility with all forms of AI models, including cutting-edge large language models and vision transformers, it ensures long-term viability and adaptability to emerging AI methodologies.

Unlike conventional architectures, the Chimera GPNPU excels by permitting complete workload management within a singular execution environment, which is vital in avoiding the cumbersome and resource-intensive partitioning of tasks seen in heterogeneous processor setups. By facilitating a unified execution of matrix, vector, and control code, the Chimera platform elevates software development ease, and substantially improves code maintainability and debugging processes.

In addition to high adaptability, the Chimera GPNPU capitalizes on Quadric's proprietary Compiler infrastructure, which allows developers to transition rapidly from model conception to execution. It transforms AI workflows by optimizing memory utilization and minimizing power expenditure through smart data storage strategies. As AI models grow increasingly complex, the Chimera GPNPU stands out for its foresight and capability to unify AI and DSP tasks under one adaptable and programmable platform.

Features
  • Hybrid architecture
  • Scalable up to 864 TOPS
  • Compatible with all AI and DSP models
Tech Specs
Class Value
Categories Processor > AI Processor
Platform Level IP > Processor Core Independent
Processor > CPU
Processor > DSP Core
Graphic & Peripheral > GPU
Multimedia > VGA
Processor > Vision Processor
Platform Level IP > Multiprocessor / DSP
Interface Controller & PHY > AMBA AHB / APB/ AXI
Platform Level IP > Processor Core Dependent
Processor > Microcontroller
Processor > Building Blocks
Processor > Processor Cores
Processor > IoT Processor
Network on Chip > Network on Chip
Wireless Communication > Digital Video Broadcast
Architecture Type Hybrid Von Neuman + 2D SIMD matrix
Instruction Word 64b, single instruction issue per clock
Pipeline Stages 7-stage, in-order
Cache Configuration Configurable Instruction cache (64/128/256K)
Local L2 Memory Configurable from 1MB to 16MB
Availability All Countries & Regions
Applications
  • Mobile devices
  • Automotive
  • Network Edge Compute
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