The Arkville Data Mover seamlessly facilitates data transfer between FPGA logic and host memory, achieving speeds of up to 60 GBytes/s (480 Gbps) in both directions. This IP provides a high-throughput, low-latency pathway that significantly reduces CPU workload by offloading data movement tasks, thus enhancing overall system efficiency. The IP supports industry-standard RTL interfaces for hardware engineers and standard APIs for software engineers, ensuring a flexible integration process.
Arkville is designed to support a dual full-duplex data movement, capable of handling up to 1 Tbps burst traffic through its AXI streaming interfaces. This robust functionality allows the immediate processing of packet streams and can accommodate a wide range of FPGA applications. The IP's vendor-agnostic RTL support extends across major FPGA manufacturers like Intel and AMD/Xilinx, helping future-proof designs against rapid technology changes.
For developers looking to explore Arkville's capabilities, Atomic Rules provides extensive example designs such as a Four-Port, Four-Queue 10 GbE or a Single-Port, Single-Queue 100 GbE setup. These examples serve as starting points for customizing unique applications, all backed by rigorous testing processes using Jenkins CI/CD workflows.
