The AES IP Core is an ultra-compact implementation of the Advanced Encryption Standard (AES), utilizing the Rijndael block cipher algorithm. It is capable of processing 128-bit data blocks using either 128-bit, 192-bit, or 256-bit keys, and is compliant with NIST FIPS-197 standards. Offering a spectrum of encryption and decryption modes such as ECB, CBC, and CTR, this core supports various data paths, allowing for an efficient trade-off between size and performance. Designed for both ASIC and FPGA implementations, the AES core is self-contained, requiring no external memory, thus providing robustness against differential power attacks through optional data masking and cycle hiding features.
