The AES IP Core delivers an ultra-compact implementation of the Advanced Encryption Standard using the Rijndael algorithm. Designed for both ASIC and FPGA applications, this core supports 128-bit data blocks with a choice of 128, 192, or 256-bit keys. It is FIPS-197 validated, ensuring that it adheres to federal standards for cryptographic security. This core is fully self-contained, requiring no external memory, and is available in various cipher modes including ECB, CBC, OFB, and CFB, making it adaptable to a variety of security needs.
