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All IPs > Analog & Mixed Signal > PLL > Aeonic Generate

Aeonic Generate

From Movellus

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Description

Aeonic Generate, part of Movellus' product family, offers a range of synthesizable, area-efficient clock generation solutions. These modules support high observability, enabling innovative approaches like per-core distributed clocking while also facilitating fine-grained droop response and DVFS innovation. The architecture is designed for broad process portability and post-silicon tunability, allowing features to adapt to different silicon conditions and application needs. Aeonic Generate is particularly beneficial for systems requiring exceptional testability and reliability, such as datacenter CPUs, AI accelerators, and automotive SoCs.

Features
  • High Degree of Observability
  • Configurable Architecture
  • Process Portability
Foundries & Process Nodes
Foundry Process Nodes
TSMC 16nm
22nm
Tech Specs
Class Value
Categories Analog & Mixed Signal > PLL
Analog & Mixed Signal > Clock Synthesizer
Graphic & Peripheral > Clock Generator
Interface Controller & PHY > CXL
Response Time Fast for DFS/DVFS control
Availability All Countries & Regions
Applications
  • Automotive Systems
  • AI Accelerators
  • 5G Systems
  • Aerospace
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