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All IPs > Memory & Logic Library > I/O Library > A TSMC 22nm Wirebond / Flipchip I/O library with dynamically switchabe 1.8V/3.3V GPIO, 3.3V I2C ODIO, 3.3V Analog Cell and associated ESD.

A TSMC 22nm Wirebond / Flipchip I/O library with dynamically switchabe 1.8V/3.3V GPIO, 3.3V I2C ODIO, 3.3V Analog Cell and associated ESD.

From Certus Semiconductor

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Description

This is an ultra-low leakage library. The GPIO has a worst-case leakage of only 425nA. It works with a wide VDDIO
supply range from 1.8V to 3.3V during system operation without the need for the customer to manually switch between high
and low-voltage modes. The GPIO cell set can be configured as input or output and has an internal 50K ohm pull-up or
pull-down resistor. It has a sleep function which - when enabled - puts the I/O into an ultra-low power state and latches the
I/O in the previous state. Cells for I/O, core power, and ground with built-in ESD circuitry are included. A power-on-control
circuit is integrated into an available VDDIO cell. The GPIO can do TX and RX up to 150MHz. ESD targets are 2KV HBM /
500V CDM with 2KV IEC 61000-4-2 system stress capability.

Deliverables
Hard IP
  • Verilog
  • GDS
  • LEF/DEF
  • Timing (Lib file)
  • Extracted netlist
  • Datasheet
  • Integration guide
Foundries & Process Nodes
Foundry Process Nodes
TSMC 22nm ULL
Tech Specs
Class Value
Categories Memory & Logic Library > I/O Library
Memory Controller & PHY > eMMC
Interface Controller & PHY > I2C
PDK Version Various
Silicon Validated Yes
In Production? Yes
Metallization 1P7M_4X1Z1U
Key I/O Standards RGMII, eMMc, ONFI, SPI, QSPI, LVCMOS, LPDDR, I2C, SMBus Ultra-Low Leakage (100's pA per cell)
Availability All Countries & Regions
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