The core implements a 40G UDPIP hardware protocol stack that enables high-speed communication over a LAN or point-to-point connection. It is ideal for offload systems demanding tasks of UDP/IP and media streaming in FPGA and RISC designs. Features include ARP request, reply, and a 32-entry ARP cache, ICMP ping reply, DHCP client engine, V3 IGMP membership messaging, IP jumbo packets, and more. The core is designed to handle exceptions of internal memory exhaustion and invalid incoming packets while maximizing internal memory usage for TX and RX burst traffic. The VHDL source code is provided on delivery.
