The core implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or point-to-point connection, ideal for offloading systems from demanding tasks of UDP/IP and enabling media streaming in both FPGA and RISC designs. It features support for ARP request, reply, and management, 32-entry ARP cache, ICMP ping reply, and DHCP client engine. It includes IP/UDP checksum generation and validation, MDIO bus access, and supports raw packets in both TX and RX. IP fragmentation and TCP hardware protocol stack companion core are available on demand. The design handles exceptions of internal memory exhaustion and invalid packets effectively. The core has been evaluated on Xilinx and Altera platforms for high performance.
