The core implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection. It is ideal to offload systems from demanding tasks of UDP/IP and to enable media streaming in both FPGA and RISC designs. The core supports ARP request, reply and manages 32-entry ARP cache. ICMP ping reply is included. The core provides DHCP client engine, which can get an IP address from external DHCP servers. The 10G UDPIP Core implements V3 IGMP membership Query/Report messaging. The UDP jumbo packets are supported as well as UDP port number filters and VLAN.\n\nIP/UDP checksum generation and validation are implemented. MDIO bus access to external device via AXI4-Lite bus is included. IP raw packets are supported in both TX and RX.\n\nIP fragmentation and TCP hardware protocol stack companion core are available on demand.\n\nThe core supports 32 RX channels and 32 TX channels. Each of the RX channels can be configured and associated with any of five RX ports. Each of the TX channels can be used to send IP packets on any of five TX Ports.\n\nThe core connects to user logic through Control Interface of AXI4-Lite buses; five RX Dedicated Ports of AXI4-Stream buses and five TX Dedicated Ports of AXI4-Stream buses.\n\nThe core connects to 10G MAC module through AXI4-Stream bus. KMX 10G MAC and PCS cores are available to our customers.\n\nThe core is designed to well handle exceptions of internal memory exhaustion and invalid incoming packets while it makes the max use of internal memory to deal with TX and RX burst traffic effectively.\n\nThere is a fully implemented reference design which is shipped with the core delivery.
