KMX 10G MAC and PCS core, which includes media access control (MAC) module, physical coding sublayer (PCS) module and physical medium attachment (PMA) module, is compliant with the IEEE 802.3ba-2010 standard. The core supports RS FEC defined in IEEE 802.3 Clause 108 with independent bit error detection and bit error correction. It connects to user logic via AXI4-Stream interface of 64 bits at 156.25MHZ and to 10G PCS core via XGMII interface of 64 bits at 156.25 MHZ. It also connects to user logic via AXI4-Lite interface. The MAC core accepts packets from user logic and generates new format packets by adding Preamble/SFD; padding zero bytes for short packets to 64 bytes; generating 32 bit CRC and padding it. It receives packets from 10G PCS via XGMII interface and generates new format packet by removing Preamble/SFD and 32 bit CRC after CRC checking. It supports Pause Frame processing for flow control and Implements Deficit Idle Count algorithm to ensure maximum possible throughput at the transmit interface. It implements internal XGMII loopback for debug purpose, which at the XGMII interface, the data flow on TX path is redirected to RX path and no data is forwarded to XGMII TX interface. It implements configuration, control, status, statistical information collection and it supports VLAN tagged frame defined IEEE 802.1Q. KMX 10G PCS module connects to 10G MAC module via XGMII of 64 bits at 156.25MHZ and connects to transceiver interface at 64 bits at 161.1328125MHZ. The PCS core is compliant with IEEE 802.3ba specifications. The core supports the following features: It implements 64b/66b encoding/decoding. The core supports 10G scrambling/descrambling of polynomial 1 + x^39 + x^58. It implements gearbox on both TX and RX. The 66-bit block synchronization algorithm implementation is included. The BIP-8 generation/insertion on TX and checking on RX are supported. It implements Bit Error Rate (BER) for monitoring excessive error ratio. The transceiver interface loopback for debug purpose is implemented, which at transceiver interface, the data flow on TX path is redirected to the RX path and no data is forwarded to transceiver TX interface. The core supports link signaling protocol.
