KMX 100G UDPIP Core implements UDP/IP protocol hardware stack that achieves high-speed communication over a LAN or a point-to-point connection, which is ideal to offload systems from demanding tasks of UDP/IP encapsulation and to enable media streaming in both FPGA and RISC designs.
The core supports ARP request, reply and manages 32-entry ARP cache. ICMP ping reply is included. The core provides DHCP client engine, which can get an IP address from external DHCP servers. The 100G UDPIP Core implements V3 IGMP membership Query/Report messaging. IP jumbo packets are supported as well as UDP port number filters and VLAN.
IP/UDP checksum generation and validation are implemented. They can be enabled or disabled. The MDIO bus access to external device via AXI4-Lite bus is included. The IP raw packets are supported in both TX and RX.
IP fragmentation and TCP protocol hardware stack companion core are available on demand.
The core supports 32 RX channels and 32 TX channels. Each of the RX channels can be configured and associated with any of five RX ports. Each of the TX channels can be used to send IP packets on any of five TX Ports.
The core connects to user logic through Control write Interface and Control Read Interface of AXI4-Lite buses; five RX Dedicated Ports of AXI4-Stream buses and five TX Dedicated Ports of AXI4-Stream buses.
The core connects to 100G MAC module through AXI4-Stream bus. KMX 100G MAC and PCS cores are available to KMX customers.
